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   Dr. Niru Kumari, Hewlett Packard
 

 

 
Resistive Memory: Energy-efficient Memory Technology
(May 10, 2016)

Energy-efficient computing devices are important foundations for sustainable IT system. The shift to big data applications makes it essential to replace power-hungry memory hierarchy of DRAM and hard-disk drive technologies with a universal non-volatile memory technology. Resistive memory is a promising candidate with desirable characteristics of low-power, crossbar architecture compatibility providing high density and fast access time. There are interesting thermal challenges in this technology including the switching mechanism driven by thermophoresis and sneak (equivalent to leakage) current strongly dependent on ambient temperature. I will present current undergoing studies to address these challenges and improve the performance of the
resistive memory.

 

 


Dr. Niru Kumari joined Hewlett Packard Co. 2010 and is currently a Senior Research Scientist in the Platform Architecture Lab at Hewlett Packard Labs,
Hewlett Packard Enterprise. She is a mechanical engineer and keenly passionate about sustainability and environment. This has led her to work on next generation IT computing systems with significantly high performance at low energy consumption. She is currently leading the thermal research on non-
volatile memory and future system on chips for the Machine, a new computing architecture for big data applications.

 


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   Dr. Alexander Yatskov, Juniper Networks
 

 

 
Comparison of HPC/Telecom Data Center Cooling Methods by Operating and Capital Expense
(April 12, 2016)

Current advanced HPC or Telecom computer systems have passed ~20kW/cabinet, i.e. 250 w/ft2. In the next 1-3 years that will likely triple to 60kW/cabinet; in 4-6 years we should expect 80-120kW/cabinet. That means power density will triple, then quadruple reaching up to 10-15 kW/ft2. The impact of that power growth is double-fold. On one hand it introduces higher power density per microprocessor (300-700W), packaged inside 1RU blade with power range of 3-5KW. On the other hand, it brings a challenge of moving that amount of heat more effectively. Regardless the existence of much more efficient, different by effectiveness, Liquid Cooling (LC) methods, there is no agreement between HPC/Telecom professionals which method has be used, due to lack of detailed bottom up comparison for the representative computer system.

Based on detailed, analysis of a ~1mW computer cluster, the presentation compares capital and operating costs associated with cooling that system by four alternative cooling options: (1) air to water/PG cooling - outside chiller; (2)water/PG touch cooling - to water- to outside air via dry cooler, (3) R134a refrigerant touch cooling - to water - to outside air via dry cooler, (4) R134a refrigerant touch cooling - to outside air via dry cooler. Optimal cooling approach, for the exactly the same size, power, layout computer system was the goal of our
study. A major outcome of current research was is in turning growing industry power norms into much more thermally efficient and lower cost data center cooling systems.

 


Dr. Alexander Yatskov is a Principal Engineer at Juniper Networks, bringing extensive experience in high technology innovation and product development. He
received his Doctor of Engineering degree from Moscow Technological University and MSEM degree from Tufts University. Prior to joining Juniper Networks, he worked as VP of Engineering at Thermal Form & Function Inc., an engineering firm developing high density cooling systems for digital and power electronics, and at Cray Inc., where he developed cooling systems for Red Storm, XT-3, XT-4, Jaguar, Titan, and other supercomputer platforms. He authored seventeen
articles and holds twenty five US patents in electronics cooling and packaging area.

 


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   Bharath Nagendran, Electronic Cooling Solutions, Inc
 

 

 
Thermal Design of Forced Convection Tablets
(March 8, 2016)

Engineering a forced convection tablet whose performance matches that of laptop computers, and yet maintaining the size and portability of a tablet, is an enormous challenge. The thermal design of such tablets involves optimizing heat flow and heat transfer paths while considering the multiple design aspects of the product.

Consumer ergonomic factors such as the form-factor of the tablet, thickness, acoustics, and touch temperature, along with safety factors such as battery temperature become crucial for a successful product. This presentation will provide a summary of these challenges, along with an overview of the experimental and computational characterization of forced convection tablets based on recent studies performed by Electronic Cooling Solutions.

 
Bharath Nagendran holds a master’s degree in mechanical engineering from The University of Texas at Arlington, and is currently working as a Thermal Engineer at Electronic Cooling Solutions Inc.. He has worked on the thermal design and analysis of a variety of products including natural convection devices such as action cameras and Wifi routers, and also forced convection systems such as servers, network switches, and telecommunications equipment.

 


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Adriana Rangel is a thermal engineer at Cisco. She has worked on CFD analysis and experimental testing of electronic equipment for 15 years, covering a wide range of products. She has extensive experience in thermal design of server and switches, and validation test design. She has a Master’s degree in Mechanical Engineering with emphasis in Thermal/Fluids engineering from San Jose State University.

 
Pressure Effects of TIM on Mechanical Assemblies
(October 13, 2015)

This presentation examines the effects of pressure on thermal interface material (TIM), not only how pressure affects thermal performance, but also what issues are encountered when TIM is under pressure when installed in a heat sink assembly.

We will look at different types of TIM and its applications, how to model TIMs and what issues can be found when TIM is over-compressed or under-compressed, along with possible solutions. We’ll also look at how different heat sink attachments affect TIM performance.

 


Gary Chan is a thermal expert in the network equipment and server industries. Gary is a Principal Engineer at Electronic Cooling Solutions, providing complete thermal solutions to a wide portfolio of clients. Prior to joining ECS, he was a Technical Leader at Cisco Systems, working on high volume forced air and natural convection switches. Before Cisco, he was a Member of Technical Staff at Hewlett-Packard. Gary received his BSME from Chico State University and his MSME from San Jose State.

 


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    Dr. Russ Westphal, Cal Poly
 

 
Recent Adventures in Thermal & Pressure Anemometry
(September 8, 2015)

As part of ongoing efforts to develop instrumentation for application to subsonic flight and wind tunnel testing, Prof. Russ Westphal’s group at Cal Poly has been exploring novel versions of pressure-based and thermal methods for anemometry. The presentation will highlight work on two projects: (1) a single-port pressure probe capable of determining both velocity magnitude and direction, and (2) the constant voltage hot-wire anemometer. Unique hardware developed as part of the work on these projects will be on display and available for up-close inspection by participants.

 

Dr. Russell V. Westphal, has over 35 years’ experience in the conduct of experimental fluid dynamics research and projects with emphasis on viscous aerodynamic flows and especially instrumentation development. Dr. Westphal’s sponsored research includes a number of past efforts for Northrop Grumman; he has also collaborated with USAF, NASA, Boeing, Pacific Northwest National Laboratory, and faculty from academic institutions including University of Arizona, Stanford, Cal Tech, Newcastle (Australia), and Cambridge (UK). He previously held the position of Chief, Advanced Aerodynamic Concepts Branch at NASA’s Ames Research Center, and served on the faculty at Washington State University and San Jose State University.
 

Currently the holder of the Constant J. and Dorothy F. Chrones Professor chair at California Polytechnic State University, he is also Donald E. Bently Professor of Mechanical Engineering and was formerly Lockheed Martin Professor of Engineering. Dr. Westphal earned MS and PhD degrees in Mechanical Engineering from Stanford University.

 


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    Mr. John Wilson, Mentor Graphics Corporation
 

 
Application of Computational Fluid Dynamics in Electronics Thermal Design
(August 11, 2015)

The Electronics industry has benefited from the application of Computational Fluid Dynamics (CFD) for over 30 years. The limitations in computational resources and available tools provided significant challenges in the application of CFD to Electronics thermal design. The typical user of CFD was required to be proficient with meshing, turbulence models, and numerical algorithms. Over that last 25 years the Electronics thermal designer has benefited from the evolution of purpose built thermal design tools that use CFD.

Today CFD is much less the focus but rather the engine that provides the most accurate predictions. While computers were getting faster and memory cheaper more technology was built into thermal design tools. Today we are able to model such things as thermal resistor networks, detailed IC packages, and multi-layer printed circuit boards, all in a system level analysis that more accurately represents the product being designed. The connectivity between the mechanical, electrical, and thermal disciplines has increased in terms of the design flow and thermal design tools support this methodology.

In this session we will take a look at the application of CFD to Electronics Thermal Design from a historical perspective up to today’s best practices. We will discuss the benefits of analysis at each phase of the design from feasibility studies to final verification.

 

John Wilson joined Mentor Graphics Corporation, Mechanical Analysis Division (formerly Flomerics Ltd) after receiving his BS and MS in Mechanical Engineering from the University of Colorado at Denver. Since joining in 1999, John has worked on or managed more than 70 thermal and airflow design projects. His modeling and design knowledge range from component level to Data Centers, heat sink optimization and compact model development. John has extensive experience in IC package level test and analysis correlation through his work at Mentor Graphics’ Fremont based Thermal Test Facility. Currently John serves as an Electronics Product Specialist.
 

 

 


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    Mr. Tom Tarter, Package Science Services
 

 
High Density IC Package Manufacturing Considerations
(July 14, 2015)

A look at current capabilities, costs and challenges when designing high-density IC packages. We will look at stackups, materials, routing, via structures, a bit on SI and PI and how and where these fine line packages can be produced. We will also discuss performance parameters and some of the tools used for design, modeling and analysis.

 

Tom Tarter is the proprietor and principal engineer of Package Science Services. He is a working professional in the area of thermal management and electrical characterization of packaging structures. He spent over 16 years at Advanced Micro Devices (Sunnyvale, CA) in package characterization and left as a Senior Member of the Technical Staff.
 

Tom has authored or co-authored over 20 published papers, and numerous short courses and lectures on thermal and electrical phenomenon in microelectronic and optoelectronic packaging. He has presented short courses and technical papers at conferences and technical meetings around the world., and as an invited lecturer and author, has also lectured at graduate level short courses on micro- and opto-electronic packaging at UC Santa Cruz extension and San Jose State University.

 


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    Mr. Henry Coles, Lawrence Berkeley National Laboratory
 

 
Survey of Data Center Efficiency and Electronics Cooling Technology
(June 9, 2015)

A survey of data center efficiency and electronics cooling technology demonstrations from 2009-present, conducted by Henry Coles at Lawrence Berkeley National Laboratory.

The technologies include: direct component cooling, rack level cooling devices, gaseous contamination in data centers, two-phase immersion cooling and server power use and efficiency comparison.

 

Henry Coles specializes in the design, testing and evaluation of computer equipment cooling solutions. Henry has experience in product and process development at Hewlett Packard, Compaq Computers, Tandem Computers and National Semiconductor. Projects at Hewlett Packard included server chassis mechanical design and thermal design and testing of containerized and rack level cooling solutions. Projects at Lawrence Berkeley National Lab. include product testing, thermal performance metric development and evaluation for the Chill-Off 2 project. He is a graduate of Stanford University (MSME 1976) and Cal Poly State University San Luis Obispo CA (BSME 1975)

 

 


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    Mr. George Meyer, Celsia Technologies, Inc.
 

 
Towards a Heat Pipe Measurement Standard
(May 12, 2015)

Testing methods currently in use in the industry are not standardized which leads to inaccurate information when trying to design thermal solutions that incorporate these products. The use of the standard will allow the direct comparison of various product designs and products from various vendors.
.
Efforts are currently ongoing within the JEDEC JC15 committee to develop a set of standards for measurement of two phase heat transfer devices. The first of these standards will focus on round heat pipes and flat vapor chambers using the traditional heater test method and the electrical test method

 

Mr. Meyer is a seasoned industry veteran with over three decades experience in electronics thermal management. He has been with Celsia since December 2005, first as VP Sales and Marketing for the Americas and Europe regions and then as COO and CTO. In these roles, Mr. Meyer has been instrumental in establishing Asian operations, developing new technologies, key customer relationships, managing the product portfolio, and growing sales into the computer, telecommunications, LED lighting, medical, and military markets.

Prior to Celsia, he held various positions with Thermacore International (a leading supplier of thermal management solutions) including chairman and general manager of ThermacoreTaiwan and Korea, as well as vice president, worldwide sales and marketing. During his tenure, Meyer was credited with establishing the company’s Asian design and manufacturing facilities, developing patentable product designs, and growing relationships with leading technology companies such as Intel, Hewlett-Packard, Apple, Sun Microsystems and Silicon Graphics. He graduated from PennStateUniversity with a degree in Communications and holds an International Business Certificate from Franklin and MarshallCollege. Mr. Meyer is also a certified 6 Sigma Black Belt and holds 94 domestic and international patents/patents pending in the field of electronics thermal management.

 


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Thermal Test Chip Application Considerations
(April 14, 2015)

Thermal Test Chips (TTC) are intended for many different applications – package design, reliability studies, thermal management design, TIM characterization, etc. The versatility of TTCs is limited only by the user’s imagination and knowledge of what can and can not be accomplished. Issues such as chip type, contacts, arraying limitations, power density, temperature sensing, chip thickness and contact spatial layout will be discussed.

 

Bernie Siegal is a 45+-year veteran and recognized technical leader in the semiconductor and electronics thermal field. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry and US military measurement standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 45 technical papers, presented seminars and short courses.
 

He has authored over 45 technical papers, presented seminars and short courses. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A., M.S.E.E., and B.E.E. degrees. He is a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field.

 


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    Mr. Youssef Elmoussaoui, JMC Products
 

 
System Impedance and Fan Selection Overview
(February 10, 2015)

Understanding system impedance curve is critical in choosing the correct fan for optimal cooling and acoustic performance of the system. This presentation
is an overview of fan selection techniques in relation to system impedance and a discussion of the various speed control and sensing features that are
offered in DC fans including software based features with serial communication capabilities.

 

Mr. Youssef Elmoussaoui, is the engineering manager at JMC Products, a leading manufacturer of DC fans and blowers. Youssef has been working for JMC for 12 years. He is responsible for the development of air moving devices with a focus on motor drive and control. Youssef has a BS in Electrical engineering from
the University of Texas at Austin.
 

 

 


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Solving Heat Sink Induced Parasitic Capacitive Coupling with Thermally Conductive Plastics
(September 09, 2014)

Dr. Jim Miller is Product Manager at Cool Polymers, Inc. He    received his Ph.D. in polymer science from Case Western    Reserve University and was a finalist in NASA’s astronaut selection. Jim was an initiator in the area of thermally conductive thermoplastics and has worked in the field for 21 years. Cool Polymers was awarded the 2003 ASM Engineering Materials Achievement Award for the development and application of injection moldable plastics with exceptionally high thermal conductivities. He also co-developed voltage contrast XPS, a spectroscopic method for quantitatively measuring fiber-matrix adhesion in advanced composites.

 

Thermally conductive plastics having conductivities up to 40 W/mK are useful as lightweight, low cost, 3-dimensional heat sinks in electronic applications. The non-metallic composition reduces or eliminates parasitic capacitive coupling common with metallic heat sinks. Typical applications for interference reduction include telecom electronics and flat screen displays. The plastic heat sinks also reduce shock and vibration loads, lessen the need for mechanical attachment, and consume only 1/3 the energy to manufacture.
 

 

 


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Design to Cost Liquid Cooling
(August 12, 2014)

In liquid cooled data centers, the promise of lower costs due to reduced air conditioning has not been fulfilled.  The problem is that current liquid cooling systems are based on complex system designs which do not lend themselves to cost reduction based on scale-up.  The electronics industry is built on the idea that complex designs can be easily cost reduced in production, but in the mechanical world cost savings are harder to achieve.
This talk will focus on the advanced liquid cooled data center power model (from Chilldyne) that includes the effects of HVAC, leakage current, server fan power and heat extraction with liquid cooled, finned heat sinks. This allows anyone to accurately determine the savings before the liquid cooling system is purchased and installed.

 

Dr. Harrington has over 27 years of commercial experience in the fields of fluid dynamics, thermodynamics and electronics cooling. His unique experience runs the gamut from consumer product development to science. Dr. Harrington has consulted for the aerospace, semiconductor, medical device, racing and other industries. He has been responsible for numerous successful product development projects and IP generations. He holds a dozen U.S. patents and is named on many more. Dr. Harrington is responsible for the design, development and analysis of the Chilldyne liquid cooling systems for data centers. He specializes in analyzing heat transfer and fluid flow using Computational Fluid Dynamics and MathCAD developing embedded software and electronics to monitor and control the system, and optimizing systems for reliability, TCO and ease of use. He has extensive experience analyzing liquid cooling systems for thermal resistance, head loss, corrosive resistance and service life. He also teaches a Senior Aerospace Design class at the University of California, San Diego where students instrument, build and fly rocket systems.

 

 


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Predictive Analytical Thermal Stress Modeling in Electronics and Photonics
(July  08, 2014)

The talk will be based on the role and attributes of, as well as the state-of-the-art and some major findings in, the area of predictive analytical thermal stress modeling in electronic, opto-electronic, and photonic engineering. The emphasis will be on packaging assemblies and structures and on simple meaningful practical models. The talk will indicate the role, objectives, merits and shortcomings of analytical modeling and discuss its interaction with FEA simulations and experimental techniques.
 

 

Dr. Ephraim Suhir is on the faculty of the Portland State University, Portland, OR, USA. He is the IEEE, ASME, APS, IoP (UK), SPE, SPIE and IMAPS Fellow, Foreign Full Member (Academician) of the National Academy of Engineering, Ukraine and Fulbright Scholar, Information and Telecommunications Technologies, Council for Intl. Exchange of Scholars, State Dept., USA. Dr. Suhir is Distinguished Lecturer of the IEEE CPMT Transactions, Member of the IEEE CPMT Award committee, CPMT & VTS IEEE Fellow nomination committees, and the ASME General Awards committee. He is the co-founder of the ASME J Elec. Packaging and served as its Technical Editor for 8 years (’93-’01). Dr. Suhir has authored about 350 technical publications, organized many successful conferences and symposia and presented numerous keynote and invited talks worldwide. He received many professional awards, including the 2004 ASME Worcester Read Warner Medal “for outstanding contributions to the permanent literature of engineering through a series of papers, which established a new discipline, known as Structural Analysis of Microelectronic and Photonic Systems”. Dr. Suhir is the 3rd ‘Russian American’, after Steven Timoshenko and Igor Sikorsky, who received this prestigious ASME award.

 

 

   

Thermal Failures in Consumer Products: Failure Analysis Techniques
(June  10, 2014)

Failure in consumer products can result in personal injury, poor product performance or environmental impact. Unfortunately, these events will occur no matter how robust the product design or how effective the reliability program. Every engineer encounters failures in their product or manufacturing process. One must therefore determine the cause of the failure to prevent future occurrence. Failure analysis is the process of collecting and analyzing data to determine the cause of a failure. This seminar will provide a logical approach and information on how to perform failure analysis specifically focusing on the thermal aspects, along with case studies.
 

 

Dr. Gopalakrishnan (Georgia Tech) is a manager in the Thermal Sciences practice at Exponent. She specializes in evaluation of consumer appliance design, performance and failures, fire cause and origin analyses and battery testing. Dr. Gopalakrishnan performs analyses involving fluid mechanics, combustion, heat transfer, thermodynamics, and fire sciences. She has extensive experience in failure analysis and performance evaluations of various household appliances, automotive equipment, heating systems, battery powered consumer electronics, lighting systems, and fire sprinklers. Dr. Gopalakrishnan has also performed several quality assessments and design evaluations of batteries with various chemistries; mechanical and thermal abuse testing of cells and battery packs, failure investigation of batteries and fire investigations of incidents involving batteries or battery powered devices.

 

 

   

The Motivating Question – Focus your experiment by identifying the motivating question
(May  13, 2014)

The Motivating Question – Focus your experiment by identifying the motivating question. Save time, save face, save money.

The talk will focus on the fundamentals of how to setup experiments, either larger or smaller ones in order to obtain meaningful results

 

Ten years in General Motors Research Labs: gas turbine heat transfer. Forty seven years in Stanford Mechanical Engineering Department: turbulent boundary layer studies, experimental methods, medical heat and mass transfer, neonatal intensive care. Electronics cooling studies began in 1977 and continued through 1994. – 4 PhD programs 

Off hours: bike riding (Monterey to LA on Hwy 1), fly fishing (29 ½ inch Rainbow on a 4-weight rod!)
 

 

 

   

Air Filter Solutions for Data Center Equipment
(April  08, 2014)

Air filter solutions and sourcing discussions on prevention of equipment failure / network downtime, energy efficiency improvements, and cost savings opportunities. Other technical information provided for equipment maintenance, UL flame safety, and NEBS (Network Equipment Building Systems) requirements for Telco networks and data center facilities. Shelf-level applications for servers, switches, and storage as well as rack-level/room-level in-row and mobile cooling units. CRAC unit and building HVAC applications also presented.

 

Mr. Dan Krupp is the Director of Sales and Engineering at Universal Air Filter. He is responsible for managing relationships with key business partners and customers while setting the overall strategy of the business. Direct and manage all sales, marketing, design engineering and product development activities. Lead engineering and sales teams focused on achieving revenue and profit goals. Areas of expertise and responsibility include: strategic planning, international technical sales & marketing, marketing and sales management, design engineering, research and development and product management
 

 

 


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How to Select a Semiconductor Package
(February  11, 2014)

Introduction to design, materials, assembly and cost attributes to consider when selecting a package for your semiconductor device. The course provides a basic understanding of packaging and processes to help engineers in all disciplines make sound packaging decisions early in the design cycle of the chip or system.
 Some of the questions that will be answered: What is the purpose of a package? What factors are required for selection? What performance factors are important? How does manufacturing affect design, performance and cost?

 

Tom Tarter is the proprietor and principal engineer of Package Science Services. He was a working professional in the area of thermal management and electrical characterization of packaging structures. He spent over 16 years at Advanced Micro Devices (Sunnyvale, CA) in package characterization and left as a Senior Member of the Technical Staff. Tom has authored or co-authored over 20 published papers and numerous short courses and lectures on thermal and electrical phenomenon in microelectronic packaging and most recently in optoelectronic packaging. He has presented short courses and technical papers at conferences and technical meetings around the world. An invited lecturer and author, he has also lectured at graduate level short courses on micro- and opto-electronic packaging at UC Santa Cruz extension and San Jose State University.
 

 

 


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John Wilson, Application Engineer , Mentor Graphics
 

Failure Prediction of IGBT Modules Based on Power Cycling Tests and Thermal Analysis
(January 14, 2014)

With the steady growth of electric and hybrid electric vehicles IGBT devices have become an increasingly popular technology that provides traction motor control.  The reliability of IGBT devices is critical to the success of this growing market.  High junction temperatures and temperature gradients directly affect the reliability of IGBT devices through thermo-mechanical stress between layers with different coefficients of thermal expansion.  In this presentation we will discuss reliability testing through power cycling, specifically die attach thermal degradation.  Further, the process of validating a simulation model from the test results will be shown and the simulation model will be used to predict potential thermal design bottlenecks.

 

John is currently the Application Engineering Manager with over 10 years of Thermal/Airflow design experience. Currently manage the Western Region Application Engineering Team responsible for consulting and test services, technical sales assistance for hardware and software solutions supporting 4 sales channels, and Tier 1 strategic account maintenance. Served as Technical or Project lead in Thermal/Airflow design and characterization lab services for over 30 Clients and 100+ projects. Projects range from the IC package to Data Center and Clean Rooms.
 


 

 


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Veerendra Mulay, Thermal Engineer , Facebook
 

Direct Evaporative Cooling Schemes in Data Centers(November  12, 2013)

The talk will focus on design of two distinct direct evaporative cooling systems employed in Facebook’s Prineville data centers in Prineville, Oregon. The two data centers use misting nozzles and wet media respectively to control the temperature and humidity of air used for cooling. The operational efficiency and challenges will be discussed.

 

Dr. Veerendra Mulay is a thermal engineer at Facebook. He is responsible for thermal management of Facebook’s data centers and hardware. As a member of hardware design team, Veerendra leads the re-engineering of Facebook’s co-location data centers resulting in significant improvement in energy efficiency. He has been supporting design and construction of Facebook’s new highly efficient data center facilities. He is also a key contributor in Facebook’s custom designed servers and other hardware.


Veerendra received his Ph.D. in Mechanical Engineering from the University of Texas at Arlington in 2009. His research was focused on cooling strategies for data centers and electronic systems. Prior to graduate studies, he worked in automobile sector as product engineer designing and developing automobile air conditioning and engine cooling components. 

 


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Bernie Siegal, Thermal Engineering Associates Inc
 

Thermal Test Chip – The Update (October 08, 2013)

As thermal management issues continue to dominate new product designs and manufacturing implementation, Thermal Test Chips (TTC) gain increasing importance as a tool for design, material, and assembly validation. This presentation will first describe TTCs and how they are used, then provide a TTC development roadmap that addresses existing and future requirements, including very high power density and Through Silicon Via (TSV) applications.

 

Bernie Siegal is a 45+-year veteran and recognized technical leader in the semiconductor and electronics thermal field. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry and US military measurement standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 45 technical papers, presented seminars and short courses.


He has authored over 45 technical papers, presented seminars and short courses. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A., M.S.E.E., and B.E.E. degrees. He is a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field.  

 


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Mr. Paul Spaan, Spaan Enterprises Inc.
 

3D Printing (Rapid Prototyping) for Thermal Applications (September 10, 2013)

The talk will cover the following points related to Rapid Prototyping for Thermal Application:
 

  • Slide Set

  • Sample Printed Prototypes

  • Operating 3D Printer

 

Paul Spaan is President at Spaan Enterprises Inc. He is an independent product design consultant for over 3 years. The company recently incorporated in 2012. He left Cisco Systems in 2009 to start his own business in 2010. The business has been doing well with mostly repeat clients. Paul has been developing computers, high end routers and switch products the last 25 years and has been developing a variety of high tech products in Silicon Valley for 35 years.
 
Since 1990, the products he helped develop at Cisco have generated over a $Billion in revenue. Products ranged from high volume 1RU rack mount products to low volume full standalone rack switch/routers. His expertise is mechanical design and has led cross-functional teams. While at Cisco he eliminated messy internal cables and replaced them with back-planes, mid-planes, and plug-in modules. He implemented cost saving processes using paperless file transfer for mfg builds. Initiated the use of hard tooling for sheet metal and plastics. And expedited proto builds thru the use of Rapid Prototyping (aka 3D printing).

 

Paul is an entrepreneur, likes to innovate and believes in staying on the cutting edge for design, prototyping and production manufacturing. His business has added 3D printing to his design services and will be adding 3D scanning in the near future. This allows him to design, iterate, and develop his own products while exploring the practically limitless possibilities of where 3D printing will take prototyping and manufacturing.

 


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Dr. Hussameddine Kabbani, Staff Thermal Engineer, nVidia
 

Thermal Challenges in Hand-Held Devices (August 13, 2013)

Hand held devices have wide functionality nowadays. The functionality of these devices is expected to be improved and expanded. However, the cost of this is more power dissipation from major chips namely the processor, wi-fi, and PMU. As a result, many thermal challenges are imposed. In this talk, power limitations will be presented, thermal challenges in mobile devices will be highlighted, and current solutions will be discussed.

 

Dr. Kabbani is currently a Staff Thermal Engineer at nVidia in the Mobile Chips group. Dr. Kabbani has vast experience in the field of thermal and fluid sciences including more than five years of experience in thermal management covering a wide range of products. He has worked on chip-level and system-level thermal management, specifically in designing and testing both passive and active cooling systems.

 

Dr. Kabbani has a Ph.D. in Mechanical Engineering, focusing on thermal and fluid sciences, from the University of Nevada, Las Vegas.

 


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Guy Wagner, Electronic Cooling Solutions
 

Investigation of the Limits of Cooling for Tablets and Cell Phones (July 9, 2013)

With the rapidly increasing performance in tablets and smart phones, the result is increased power consumption leading to devices that are uncomfortably hot to hold. This is especially true when watching video or playing games since these operations are both CPU and graphics intensive. This presentation explores the limits of cooling for handheld devices based on both testing and simulation under various conditions and provides guidelines for maximizing the amount of power that can be dissipated in these small form-factor devices. 

 

Mr. Guy Wagner is currently the Director at Electronic Cooling Solutions. He has over 39 years experience in the electronics industry. His experience includes: IC and system cooling, IC packaging technology, disk drive design, computer system design, and design of telephone switching systems. Mr. Wagner, an expert in cooling of electronics systems ranging from handheld devices to data centers, has authored 22 papers and presentations at international conferences on this subject and holds 27 patents.

 

Before joining Electronic Cooling Solutions, he held positions as a Director of Engineering at Cornice Inc.; Chief Scientist for the HP/Agilent Technologies PolarLogic Business unit and Member of Technical Staff at AT&T Bell Laboratories.
 
Guy has a Master of Science degree in Mechanical Engineering from Iowa State University.

 


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Fred Taylor, Airflow Measurement Systems
 

Applications of Air Moving Devices (June 11, 2013)

The presentation will focus on the basics of heat transfer, laminar and turbulent flow and fans/blowers and their interaction in a system.

Topics include basic air movers, most efficient operating point, and effect on noise and power draw.

 

Fred has over 40 years experience in air movers and heat transfer working for Rotron, Inc., IMC Magnetics, and Wakefield Engineering with recently spending 30 years at Ametek Rotron designing custom cooling for military electronics.

Fred is currently retired from Ametek Rotron and running Airflow Measurement Systems on a full time basis manufacturing airflow test chambers (flow benches). Fred has an undergraduate degree from the State University of New York and a Masters in Mechanical Engineering, specializing in fluids and heat transfer, from Union College in Schenectady, NY.


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Dr. Ephraim Suhir, Electrical Engineering Dept, University of California, Santa Cruz, CA, USA
 

Thermal Stress Failures in Electronics and Photonics: Prediction and Prevention (February 12, 2013)

The role and attributes of, and the state-of-the art and some major findings in, the field of thermal stress modeling in electronic and photonic engineering are addressed. The emphasis is on simple and practical models that can be and have been used in the physical design and reliability evaluations of electronic and photonic assemblies, structures and packages. We indicate the role, objectives, attributes, challenges, merits and shortcomings of analytical thermal stress modeling, and its interaction with numerical, primarily finite-element, modeling and experimental techniques.

 

Dr. Ephraim Suhir is on the faculty of the Electrical Engineering Dept, University of California, Santa Cruz, CA, USA. He is IEEE, ASME, APS, IoP (UK), SPE, SPIE and IMAPS Fellow, Foreign Full Member (Academician) of the National Academy of Engineering, Ukraine and Fulbright Scholar, Information and Telecommunications Technologies, Council for International Exchange of Scholars (CIES), State Department, USA. Dr. Suhir is Distinguished Lecturer of the IEEE CPMT Society, Associate Editor of the IEEE CPMT Transactions, Member of the IEEE CPMT award committee, CPMT and VTS IEEE Fellow nomination committees, and the ASME General Awards committee. He is a co-founder of the ASME Journal of Electronic Packaging and served as its Technical Editor for eight years (1993-2001).

 

Dr. Suhir has authored about 300 technical publications, organized many successful conferences and symposia and presented numerous keynote and invited talks worldwide. He received many professional awards, including 2004 ASME Worcester Read Warner Medal “for outstanding contributions to the permanent literature of engineering through a series of papers…which established a new discipline known as the Structural Analysis of Microelectronic and Photonic Systems”. Dr. Suhir is the third “Russian American”, after Steven Timoshenko and Igor Sikorsky, who received this prestigious ASME award.


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Sergio Escobar, Post-doc, HP Labs
 

Achieving Large Heat dissipations through Boiling of Sprays (December 11, 2012)

Spray cooling has potential to dissipate high heat fluxes; however the complexity of the heat transfer and fluid dynamics presents difficult challenges to implement it at a practical level. This talk is oriented towards a better understanding of the liquid film thickness to obtain high heat fluxes.

 

Sergio Escobar got his BS in mechanical engineering at the Universidad de Guanajuato, Mexico, 1997, later he got a MSME at the University of Puerto Rico 2000, and recently, 2012, his PhD from Santa Clara University. During his Master studies, his work on Laser Induced Fluorescence was acknowledged as the most significant paper presented to the Institute of Liquid Atomization Systems and Sprays 1999. In 2008 he was awarded the student member of the year in 2008 by the ASME EPPD. Currently he is working for Hewlett Packard as a post doc in the area of liquid cooling and energy analysis.

 

Currently he is working for Hewlett Packard as a post doc in the area of liquid cooling and energy analysis.


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Herman Chu, Principal Engineer, Cisco Systems
 

Evaluating Heat Pipe and Vapor Chamber Solutions for Practical Applications (October 9, 2012)

Heat pipes and vapor chambers have been proliferated in the high-volume computer industry in the past decade. While these technologies are not new, their fabrication processes have been improving allowing thinner base and increased fin surfaces.
 
In this short talk, the practical limits of using conventional solid metals will be analytically compared to 2-phase conduction devices, empirical test processes will also be discussed along with the performance results. The key parameters for evaluating these technologies will also be reviewed.

 

Herman Chu is a Principal Engineer at Cisco Systems focusing on process and strategy developments for thermal and acoustic designs; he is also working on green initiatives for network equipment both at Cisco and in the industry. He is classically trained in thermal fluid systems and has over 25 years of industry experience that spans from military aerospace applications to electronic cooling of consumer products, computers and computer servers, mainframes and network equipment.

 

His current passion is to educate and drive reduced power designs for electronics for both within Cisco and the industry.


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How to Choose the Right Fan for your Application (September 11, 2012)

An explanation of fan performance parameters with the goal of enabling more informed selection decisions. The importance of a system level approach to optimizing fan based thermal solutions early in the design cycle.

 

Nigel Strike is a Principal Engineer with NMB and have been with them for 20 years first in the UK and for the last 9 years out of our US Arizona facility. He have been involved with fan design for military, industrial and commercial applications for most his career his main focus being motor drive design. Currently, He is managing the development of large fan product (>6” dia) in the US and provide customer and sales technical support.

 


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John R. Thome, EPFL, Switzerland
 

Basics of Two-Phase Microchannel Electronics Cooling (August 14, 2012)

The presentation will provide a basic overview on the status and issues of flow boiling in multi-microchannel cold plates for electronics cooling (CPU’s, IGBT’s). Videos of the two-phase flows, use of micro-orifices to steady and distribute the flow, heat transfer and pressure drop simulations, choice of coolants, two-phase cooling system designs and their energy consumption, etc. will be presented. The idea is to incite an open discussion on the future role of two-phase cooling.

 

John R. Thome is Professor of Heat and Mass Transfer at the Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland. An American, he received his Ph.D. at Oxford University and was then an Assistant/Associate Professor at Michigan State University, leaving to start his own consulting company at the age of 31, and returning to academics 15 years later to join the EPFL in 1998. He has authored four books on two-phase heat transfer, widely used in refrigeration, air conditioning, electronics cooling, nuclear, and chemical engineering.

 

He received the ASME Heat Transfer Best Paper Award, UK Institute of Refrigeration J.E. Hall Gold Medal, and ASME Heat Transfer Memorial Award. He directs the Laboratory of Heat and Mass Transfer with 20 PhD’s and post-docs and hosts a Microscale Heat Transfer Summer School each June in Lausanne.

 


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Adriana Romero, Thermal Engineering Manager, Electronic Cooling Solutions, Inc.
 

Cooling Switch Blades with High Power Optical Modules (June 12, 2012)

Optic Modules have unique thermal constraints because the laser reliability is dependent on temperature. The module cannot be permanently attached to a heatsink so that it can be removed. A riding heatsink is typically deployed to mate to the module, but considerable thermal contact exists between the module and the heatsink. This study investigates a series of Flotherm models that attempt to cool a 5-Watt Quad Form Factor Pluggable (QSFP) optical module.

 

Adriana Romero is a Thermal Engineering Manager at Electronic Cooling Solutions. She has worked on CFD analysis and experimental testing of electronic equipment for more than 10 years, covering a wide range of products. She has extensive experience in thermal design of server and switches and in validation test design.

She has a Master’s degree in Mechanical Engineering with emphasis in Thermal/Fluids engineering from San Jose State University.


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Dr. Kenneth Goodson, Professor and Vice Chair of Mechanical Engineering, Stanford University
 

Nano Thermal Engineering for Electronics (May 8, 2012)

The market is driving major challenges for electronicsl thermal management involving high-performance portables, 3D integration, and nonvolatile memory. This motivates an unprecedented level of nano research – ranging from basic thermal conduction phenomena and metrology to nanostructured heat sinks – in the academic community. Stanford activities include nanostructured packaging materials, nano/picoscale thermal metrology, thermoelectric energy conversion, and phase change random access memory (PCRAM). This presentation summarizes our research in these areas and highlights nearly 20 years of collaboration with Silicon Valley companies.

 

Dr. Kenneth Goodson (nanoheat.stanford. edu) is Professor and Vice Chair of Mechanical Engineering at Stanford. Goodson (MIT Ph.D. 1993) has co-authored 150 archival journal articles, 200 conference papers, 30 US patents, and two books. His 34 doctoral alumni include professors at MIT, UC Berkeley, UCLA, and Stanford as well as staff at Intel, AMD, IBM, and Applied Materials.

Goodson is an ASME Fellow and received the Allan Kraus Thermal Management Medal and SEMITHERM Best Paper Award. Keynote and plenary appearances include INTERPACK, ITHERM, SEMITHERM and THERMINIC. Goodson is a founder and former CTO of Cooligy, which builds microfluidic heat sinks and was acquired by Emerson in 2005.


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Dr. Sai Ankireddi, Senior Engineering Manager, Intersil
 

Statistics-Based Design Paradigms For Microelectronics Packaging (April 10, 2012)

Most design approaches for microelectronics packaging- whether they pertain to cooling design, material selection, structural construction or assembly- are based on deterministic, and often worst case scenarios. Such approaches can often lead to unnecessary BOM cost increases, lengthy design cycles, unneeded conservatism in the final product, and in the worst case a missed market window. In this presentation we’ll introduce the concept of statistics-based design, and apply it to illustrative examples for CPU cooling, BGA packaging, server cooling and datacenter planning to demonstrate the key competitive advantages of such a design philosophy.

 

Sai Ankireddi is Senior Manager, Package & Assembly Engineering Group at Intersil Corporation. His group focuses on wafer level packaging, copper wire-bonding development and high density leadframe array packaging for consumer and power management analog ICs. Prior to Intersil, Sai was with the Microelectronics Packaging group at Sun Microsystems where he drove the development of flip-chip packaging for the UltraSPARC family of microprocessors/ASICs in deep sub-micron process lithography nodes.

He has served as past General Chair of SEMITHERM, serves on SEMI-THERM’s Steering Committee and is actively involved in activities of the ECTC, serving on its Assembly & Manufacturing Technology Committee. Sai is an active participant in industry conferences and consortia, with 30+ published papers in multidisciplinary areas and several issued/pending patents. He also serves as Guest Associate Editor for the IEEE Transactions on Components and Manufacturing Technology.


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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
 

The Art of TIM Thermal Measurements (March 13, 2012)

As the importance of understanding of electronic system thermal characteristics has grown, the need for making proper thermal measurements following a reasonably standardized approach has become paramount. In the area of Thermal Interface Material (TIM), whether used inside the semiconductor package (TIM0) or external to the semiconductor package (TIM1 or TIM2), there are two approaches to thermal measurements; standards-oriented or applications-oriented. Both of these approaches make use of a temperature change in the measurement environment but differ primarily in which temperature changes and how the measurement environment is configured. Both approaches have there place as they provide two different types of results. The standards-oriented approach primarily focuses on measurement of a key TIM attribute - thermal conductivity (kT). This is an attribute of the bulk material, devoid of Bond Line Resistance (BLR), and is useful in comparison of materials and, through calculation, determining material specific heat. The key standard for the kT measurement currently appears to be ASME ASTM-D5470 test method. The applications-oriented approach concentrates on how the TIM is used and makes a thermal measurement that more closely reflects actual usage of the material. An example of this approach is making a thermal resistance measurement from the semiconductor junction to the heat sink, with TIM1 applied between the top of the semiconductor package and the bottom of the heat sink. This presentation will deal with both approaches, describing how the measurements are made, what data is important, and how to get the desired results.

 

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUniversity), M.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.


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Dustin Kendig, VP of Engineering, Microsanj
 

Thermal Imaging of Electronic and Optoelectronic Devices (February 14, 2012)

Thermal characterization on a micron scale is an emerging challenge for electronic and optoelectronic device development. Junction temperatures are no longer a meaningful measurement since multiple hotspots exist on a die. Space limitations on the die preclude the use of embedded thermal sensors for thermal characterization. Full field thermal imaging technology on the other hand, provides rich information to enable visual detection of irregularities beyond what can be detected with spot temperature measurements.

Thermoreflectance imaging is a method for quickly obtaining a thermal image on micron-scale devices with excellent spatial and temperature resolution. The uniqueness and benefits of the thermoreflectance technique are introduced with the NT200-Series Thermoreflectance Image Analyzer and the SanjVIEWTMsoftware package.  Examples include the thermal imaging of a CMOS thermal test chip from TEA Inc., in a wire-bond package and a flip-chip package (with through-silicon imaging). The transient response of the built-in heaters provides a footprint of the chip’s thermal profile. These thermoreflectance images are compared with conventional infrared (IR) images on the same samples. The example further explores other types of devices, such as LEDs, micro coolers, micro vias, and solar cells. The thermal images help to identify potential defects that affect reliability in devices with submicron features.

 

Dustin Kendig graduated Cum Laude from the University of California Santa Cruz with a B.S. in Electrical Engineering in 2009. His university research focused on high resolution thermal imaging and the characterization of defects in solar cells. He is the author or co-author in more than 10 journal and conference papers. He was the winner of the Huffman Prize, Dean’s Award, and Chancellor’s Award in 2009 at UCSC. Dustin is a member of the Engineering Honor Society Tau Beta Pi.

 


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David Nelson, Principal Consultant, Nelson Acoustics
 

Forecasting Noise Emission and Power Consumption of Fan-cooled Devices (January 10, 2012)

Acoustic noise emission requirements are tightening and power densities are generally increasing. While seeking to provide adequate cooling airflow, thermal engineers need to know the consequences of various design choices such as fan type, diameter, number, flow-path back-pressure and inlet conditions. Noise Acoustics uses an empirical method based on general design parameters to quickly evaluate various configurations and to help steer towards an optimal solution in which all requirements are met.

 

David Nelson has thirty years of experience in fan noise, product design, sound quality, and many other diverse aspects of acoustics. He is Principal Consultant of Nelson Acoustics, located in the Austin, Texas area. He is a recognized expert in the area of low-noise cooling fan implementation, and as a consultant enjoys distilling otherwise obscure and complex science into clear, practical guidance. He is Board Certified by the Institute of Noise Control Engineering.

He is a recognized expert in the area of low-noise cooling fan implementation, and as a consultant enjoys distilling otherwise obscure and complex science into clear, practical guidance. He is Board Certified by the Institute of Noise Control Engineering.


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Dr. Greg Xiong, Research Scientist, Senior Staff Engineer at NetApp Inc
 

Thermocouple Attachment Using Epoxy in Electronic System Thermal Measurements (November 15, 2011)

Thermocouples are widely used in electronics thermal measurement but the often-neglected question is how good the results are? In this presentation we defined two parameters to analyze the error introduced by thermocouple attachment. A total of eight parameters that could affect data accuracy were investigated. The error was found to be 25 ~ 40% in some cases, however, a number of means can be taken to minimize it. Thermal engineers can use findings from this study to achieve their best practice.

 

Dr. Greg Xiong is a senior staff engineer at NetApp Inc., where he has been responsible for the company's thermal research and development activities since year 2000. Prior to NetApp, he had worked at Rockwell Science Center, and spent a number of years at various US universities with research projects funded by the US NAVY, AFOSR and NASA.

Dr. Xiong is the author of more than 20 external publications in peer-reviewed international conferences and journals, 2 US patents, and over 200 internal technical reports. Dr. Xiong holds a Ph.D. degree from Tsinghua University, Beijng, and B.E. degree from Shanghai Jiaotong University.


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Dr. Niru Kumari, Research Scientist, Sustainable Ecosystem Research Group at HP Labs
 

Holistic Multiscale Modeling of Data Center Energy Costs (October 11, 2011)

The rising energy consumption in the data centers is a topic of growing concern due to related cost and environmental impacts. The talk will review an end to end physical model that can be used to design and manage dense data centers and determine the cost of operating a data center. The model is used to explore impact of various management choices such as elevated data center air temperature and aisle containment on data center energy costs.

 

Dr. Niru Kumari is a research scientist in Sustainable Ecosystem Research Group at HP Labs in Palo Alto, CA. Her research is focused on energy and thermal management of sustainable data centers. She holds a MS and PhD from Purdue University in Mechanical Engineering where her research involved nanotechnology, superhydrophobic surfaces, electrowetting and electronics cooling.

 


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Thomas S. Tarter, Package Science Services LLC
 

Hot Spots: Methods for Detection and Analysis (August 9, 2011)

Thermal problems are common in today’s world of high performance devices. Chips are getting smaller and power density is going up. Due to these common phenomena and the ever increasing need for smaller, faster devices many problems that could be overlooked in the past are now becoming production roadblocks. The primary focus of this talk is how to find problems in packages related to heat transfer and cooling. These problems are not bulk issues or catastrophic material failures which are typically moderately simple to identify, but rather small failures or process defects which may not be easily identified. This talk will discuss failure analysis methods to find defects such as voids in die attach or under fill layers, package structural problems and other issues that impede heat flow in packaged IC’s. I will discuss analytical methods such as acoustic microscopy, x-ray and test techniques for design and assembly verification in the development and production modes and what reliability tests can be used to accelerate the defect propagation or failure mode exacerbation. The talk will detail the approaches for analysis, the limits of the equipment and methodology and some ideas on how to fix the problem once it is identified.

 

Thomas S. Tarter is an expert on thermal management, thermal and electrical characterization, and design of microelectronic and optoelectronic packaging structures. He spent 17 years at AMD in package characterization and was a Senior Member of the Technical Staff. Subsequently he was Director of BGA Package Engineering and Design at Advanced Interconnect Technology, and Principal Engineer for thermal management, temperature control and package development at NeoPhotonics Corporation, Inc.

In 2009, Tom started Package Science Services LLC, to serve the high-tech community with electronic packaging expertise in design, analysis, and characterization (electrical, thermal, reliability) and support all phases of IC, solar cell, LED and other chip packaging from concept to hand off to mass manufacturing. Tom has published 30 papers, holds 5 patents, and has presented numerous short courses and lectures. He chaired the JEDEC JC15.1 task group on thermal standards for five years, was general chair of SEMI-THERM, Technical Chair for five years, and serves on the SEMI-THERM executive committee to date. Tom is a senior member of IEEE and was chair of the IEEE Santa Clara Valley Chapter of CPMT for two years. Society affiliations include, IEEE, LEOS, Santa Clara Valley Nanotechnology Council, MEPTEC, IMAPS, and SPIE.


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Nate Hanlon, Applications Engineer, Mechanical Analysis Division, Mentor Graphics
 

LED Based System Thermal Design Methods (June 14, 2011)

Thermal management is said to be the most critical aspect of LED system design. Elevated operating temperatures can decrease an LED's luminous efficacy, cause color shifts, and reduce the device's lumen maintenance. Thermal management of LED systems require increased consideration due to the operating temperature's direct influence on LED optical performance. The operating temperature also directly effects the amount of heat that needs to be efficiently rejected by the thermal design.

In this presentation we will discuss in more detail the unique challenges related to developing a LED based system thermal design. We will also cover the role of measurement and analytical methods during the various phases of the design.

 

Nate Hanlon is an Applications Engineer working in the Mechanical Analysis Division of Mentor Graphics, where he works with Mentor Graphics CFD tools to perform thermal and airflow analysis on a wide range of engineering problems including electronic systems, data centers and clean rooms. Nate is also the Mechanical Lead at Mentor Graphics' San Jose based Thermal Test Facility.

Nate achieved his Mechanical Engineering Degree from San Jose State University in May 2007. Nate has spent the last 5 years working for Mentor Graphics Corporation, Mechanical Analysis Division (formerly Flomerics Ltd) specializing in the application of CFD to the design of the built environment and electronic equipment. Prior to this he worked as a lab technician for Comair Rotron in San Diego CA.


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Dr. Robert J. Moffat, Stanford University
 

Uncertainty Analysis: Living with Measurement Error and Uncertainty (May 10, 2011)

Uncertainty analysis has moved into prime time in the last 20 years. People at every level of every company that makes and sells product worry about measurement error and uncertainty – and they should! After all, customers will complain about your product if it doesn’t meet specs when they test it. It is important to be able to talk sensibly with them about the test measurement and uncertainty in order to support your claims.

Fortunately, uncertainty analysis is NOT the exclusive domain of statisticians – it fits well into the lives of test engineers and is a great help in developing good test methods. Uncertainty analysis, as a practical engineering tool, is done with a simple spreadsheet. It is 99% judgment (What are the input uncertainties?) and 1% statistics (the RSS combination).

We will take a quick look at the sources and types of error in test measurements, and illustrate the present approach with some examples from electronics cooling and gas turbine testing. Everything discussed is consistent with PTC 19.1 and its derivatives. All of this in 45 minutes!

 

Dr. Robert J. Moffat is a Professor of Mechanical Engineering (Emeritus) at Stanford University and President of Moffat Thermosciences, Inc.   Prof. Moffat started his professional career in the Gas Turbine Laboratory at General Motors Research Laboratories upon graduation from the University of Michigan.   After 10 years at GMR, he left for graduate studies at Stanford University, completing the requirements for Master of Science and Ph.D. in Mechanical Engineering. He was appointed Acting Associate Professor, 1966, Associate Professor, 1967, and Professor of Mechanical Engineering, 1972. He served as the Director of the Thermosciences Industrial Affiliates Program from 1967 to 1986 and as Chairman of the Thermosciences Division from 1973 to 1986.

 

His research efforts have involved three areas: convective heat transfer in engineering systems, experimental methods in heat transfer and fluid mechanics, and biomedical thermal issues.
Professor Moffat was an invited lecturer for 40 consecutive years in the Measurement Engineering Series (originally through Arizona State University), for more than 20 years in the Instrument Society of America Test Measurements Division Professional Development Program and, for ten years, in the ASME Professional Development program.


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Dr. Younes Shabany, Director of Thermal Engineering & Design and Thermal Architect, Flextronics International
 

New Thermal Management Drivers; What Roles Global EMS Companies Play? (April 12, 2011)

Electronic devices and systems have gone through aggressive miniaturization and extensive performance improvement in the last two decades. Despite the significant progress in material engineering and power management techniques, this has been accomplished by an increase in their power consumption and operating temperature. The effects of high temperature, and temperature variation, on accelerating electrical and mechanical failures and reducing reliability of electronic devices have been well known. That is why thermal management has been a critical design element for the realization of high-power density electronic systems. However, in recent years, other drivers of thermal management have become as important as failure prevention and reliability improvement. Some of these new thermal management drivers are power saving or energy efficiency, acoustic noise reduction, consumer comfort, and cost reduction. These new thermal management drivers, their relative importance in different markets, and the role that global Electronic Manufacturing Services companies play will be discussed in this talk.

 

Younes Shabany received his BS in mechanical engineering from Sharif University of Technology in Tehran, Iran, in 1991. He then went to Vancouver, Canada where he obtained his MS in mechanical engineering from the University of British Columbia in 1994. He came to the United States and received a Ph.D in mechanical engineering with a minor in aeronautics and astronautics from Stanford University, California, in 1999. Dr. Shabany has over 18 years of experience in thermal-fluid engineering. He is currently Director of Thermal Engineering & Design and Thermal Architect in Advanced Technology Group at Flextronics International USA, Milpitas, California. In this position, he has been leading thermal design activities in Flextronics’ worldwide design centers on a variety of infrastructure, computing, consumer, automobile, medical, and power electronic products.

 

Before Flextronics, he worked for Applied Thermal Technologies, Santa Clara, California, where he was the director for two years. While at Applied Thermal Technologies, he worked with over 60 companies and designed thermal solutions for about as many pieces of electronic equipment including telecom and networking equipment, desktop and laptop computers, biomedical equipment, and consumer products. Dr. Shabany has also been a lecturer at San Jose State University, California, since the summer of 2001. He has taught undergraduate and graduate courses in heat transfer and advanced mathematical analysis including his most favorite course, Heat Transfer in Electronics. He has also advised graduate students on their projects and theses.


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Ernie Thurlow, Thermal/Mechanical Design Engineer, Volterra Semiconductors
 

Thermal Design Considerations and Simulations for Small Integrated Power Devices (February 8, 2011)

Integrated power supplies are now widely used for various laptop, server, and graphics’ cards voltage rails since they require much less space and footprints than previously used solid state power supplies. However a consequence of a smaller footprint is a more complicated cooling design. Even though heat fluxes may only approach 50W/cm2 , limited space and footprint size limit direct convection, radiation, and heatsinking for the chip package so use of heat conduction paths to the primary layer, thermal vias, and FET power layout is critical to meet thermal requirements. This presentation will focus on different cooling techniques and practices of integrated power supply chip packages and thermal issues commonly encountered with such chip packages. The outline of this discussion will include the following; thermal resistance of a power supply chip package system, nonuniform FET power distribution, conduction paths to the pcb primary layer, thermal vias (common shapes and sizes) and heat conduction to remaining pcb copper layers, and multiphase package cooling.

 

 

Ernie is currently working as the thermal/mechanical design engineer at Volterra Semiconductors in Fremont, CA Volterra Semiconductors supplies integrated power supply chip packages to most laptop, server, graphics, and desktop manufacturers including HP, Lenovo, Alcatel, IBM, AMD, and Nvidia. Prior to working at Volterra Semiconductors, Ernie was a thermal design engineer at Nokia, Mountain View, CA and Applied Thermal Technologies in Santa Clara, CA.
At Nokia he led the 1U-3U firewall server thermal designs and participated in the mobile handset thermal design. At Applied Thermal technologies he was a consultant for several companies in the Silicon Valley including Cisco, Apple, HP, Force 10 Networks, Nvidia, BioRad, Rambus, Tyco Electronics, ATI, and Sun Microsystems.

He received his Bachelor of Science Degree in Mechanical Engineering with a specialty in Thermal/Fluid science from Washington State University in 1989, his Master of Science Degree in Aeronautical/Aeroacoustical Engineering from George Washington University and NASA Langley Research Center in 1992, and his Doctor of Philosophy Degree in Mechanical Engineering with a specialization in Fluid Mechanics Measurements in 1996 from University of Utah. He enjoys windsurfing and being outdoors and has been teaching part time for San Jose State University’s Mechanical and Aerospace Engineering Department for eleven years.


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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
 

Thermal Test Chips & Thermal Test Vehicles – Tools for Thermal Management Design (January 11, 2011)

Increasing device complexity, greater power densities, ever changing packages, and shorter time-to-market deadlines have combined to make thermal characterization efforts more frenzied than ever. A thermal test chip was designed to assist the thermal engineer in answering critical thermal packaging or material questions. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scalable array size. This allows a single wafer to supply various array sizes to meet changing requirements. This presentation will describe the key elements of a thermal test chip that meets these requirements in the simplest manner possible and the packaging of the chip into test vehicle for practical applications.

 

 

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUniversity), M.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.


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Prof. Ali Shakouri, University of California, Santa Cruz
 

Nanoscale Thermo Electric Energy Conversion Devices and Measurements (November 9, 2010)

Energy consumption in our society is increasing rapidly. A significant fraction of the energy is lost in the form of heat. In this talk we introduce thermoelectric devices that allow direct conversion of heat into electricity. Novel metal-semiconductor nanocomposites are developed where the heat and charge transport are modified at the atomic level. Theory and experiment are compared for the case of embeddded nanoparticles in a semiconductor matrix as well as in multilayer films. Potential to reach energy conversion efficiencies exceeding 20% and the trade-off between material cost and system efficiency are discussed. We also describe how similar principles can be used to make micro refrigerators on a chip with cooling power densities exceeding 500 watts per centimeter square. Finally, we describe some recent advances in nanoscale thermal characterization and modeling. Thermoreflectance imaging is used to measure the transient temperature distribution in power transistors, interconnect vias, solar cells and LEDs with down to 800ps time and submicron spatial resolution. In analogy with image blurring, a new technique is developed to estimate the temperature profile in integrated circuit chips with calculation speeds hundreds of times faster than the standard finite element methods. Comparison with the state-of-the-art architecture level thermal simulators such as HotSpot and Sesctherm is given.

 

 

Ali Shakouri is Professor of Electrical Engineering at University of California Santa Cruz. He received his Ph.D. from California Institute of Technology in 1995. His current research is on nanoscale heat and current transport in semiconductor devices, high resolution thermal imaging, micro refrigerators on a chip and waste heat recovery. He is also working on a new sustainability curriculum in collaboration with colleagues in engineering and social sciences.

He has initiated an international summer school on renewable energies sources in practice. He is the director of the Thermionic Energy Conversion center, a multi-university collaboration aiming to improve direct thermal to electric energy conversion technologies. He received the Packard Fellowship in Science and Engineering in 1999, the NSF Career award in 2000 and UCSC School of Engineering FIRST Professor Award in 2004.


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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
 

Solar Photovoltaic Cells from a Thermal Perspective (October 12, 2010)

One of the key power generation technologies in the current "green" revolution is the solar photovoltaic cell (SPVC). This unit directly converts solar energy into useful amounts of electrical energy in an increasingly economically-efficient manner. But the SPVC is not a new device - in semiconductor device terms, it is just a diode, and has been around for many decades. The newness of the SPVC lies in the increased energy conversion efficiencies and the ability of industry to find ways to lower the manufacturing and implementation costs while improving the performance and reliability. A key element in the performance and reliability improvements has centered on better control of the cell's junction temperature (TJ). This presentation will cover different types of SPVCs, SPVC performance limiters, incident power considerations, and a thermal measurement approach.

 

 

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUniversity), M.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.


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Bob Seese, Chief Data Center Architect, Advance Data Center
 

Operational Considerations in Managing Complex Thermal Environments (September 14, 2010)

Air management is now the single most critical environmental concern of data center operators. Providing robust solutions that reduce this burden while addressing the growing global concerns for energy efficiency are the challenges facing vendors at every level of the facility design as well as the entire IT stack. Constant equipment churn, increasing rack heat densities, technology refreshes and planning for changes in a manner that provides for smooth uninterrupted operations of the environment are only some of the daily challenges faced by data center operators. A few ideas for improvements to existing infrastructure products that will help increase the effective management of these environments will be presented. Vendors that address these concerns will be able to clearly differentiate their products from competitors.

 

With more than 20 years of global data center design, project engineering, and project management experience, Bob Seese has worked extensively in the mission-critical facility, facility management, and construction industries. Formerly the Chief Data Center Architect with EDS and the Director of Data Center Development with Equinix, he has managed numerous data center projects and has helped design many of the world's cutting edge facilities. While with Netscape and AOL, Bob helped design and build more than 300,000 square feet of data center space throughout the U.S. More recently, as a data center consultant, he has provided design assistance and training as well as end-to-end project support for engineers and end-users worldwide.


He has authored and co-authored numerous technical articles and presented to groups and organizations globally on issues related to energy efficiency in mission-critical environments, and on specific data center design concepts. He has completed in excess of 800 data center audits worldwide and has amassed a vast library of the "best and worst practices" in the design and operation of those facilities.

As a recognized leader in energy conservation, he participated in the San Jose Green Building Task Force and was later appointed by the mayor to a blue ribbon task force charged with evangelizing and implementing the city's first green building initiative. He actively participated in the Rocky Mountain Institute's Integrated Design Charrette, which resulted in the publication of the often quoted "Design Recommendations for High-Performance Data Centers". And, as a founding member of the Critical Facility Roundtable, Bob has continued to promote energy efficient design particularly in mission-critical environments.

Bob holds a Master's degree in Mechanical Engineering and a PhD in Educational Management, as well as Bachelor's degrees in Motion Pictures and Television and Liberal Arts.


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Thomas S. Tarter, Package Science Services LLC
 

Stacked Chip Technology Powers Up (August 10, 2010)

Chip stacking has been a part of integrated circuit technology for longer than most realize. One area where great difficulty in removing heat is found is in the stacking of chips in a single package. As 3D packaging was proven as a reliable system with potential cost savings, more designs were developed beyond the single-chip stack to system-in-package designs. Thermal management considerations for these packages become complex, due to the chips in the middle of the stack having no direct path for heat flow to the ambient. Thermal problems due to high-power chips anywhere in the stack and the inability to dictate the ‘order’ of the stacked chips create challenges in cooling. Recently, through-silicon via interconnection (TSV) has been developed to interconnect stacked chips without the constraints of wire bonding. The TSV approach makes the 3D stack even more compact, but exacerbates thermal management problems. Currently there are no standard approaches for cooling stacked chips due to the multiple types and approaches being taken. This talk will focus on removing heat from TSV stacked chip packages and will discuss methods and techniques for thermal management of stacked-chip packaging.

 

Thomas S. Tarter is an expert on thermal management, thermal and electrical characterization, and design of microelectronic and optoelectronic packaging structures. He spent 17 years at AMD in package characterization and was a Senior Member of the Technical Staff. Subsequently he was Director of BGA Package Engineering and Design at Advanced Interconnect Technology, and Principal Engineer for thermal management, temperature control and package development at NeoPhotonics Corporation, Inc.

In 2009, Tom started Package Science Services LLC, to serve the high-tech community with electronic packaging expertise in design, analysis, and characterization (electrical, thermal, reliability) and support all phases of IC, solar cell, LED and other chip packaging from concept to hand off to mass manufacturing. Tom has published 30 papers, holds 5 patents, and has presented numerous short courses and lectures. He chaired the JEDEC JC15.1 task group on thermal standards for five years, was general chair of SEMI-THERM, Technical Chair for five years, and serves on the SEMI-THERM executive committee to date. Tom is a senior member of IEEE and was chair of the IEEE Santa Clara Valley Chapter of CPMT for two years. Society affiliations include, IEEE, LEOS, Santa Clara Valley Nanotechnology Council, MEPTEC, IMAPS, and SPIE.


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David Copeland, Thermal Engineer, Oracle's Microelectronics Group - Packaging Technology Department
 

Leakage Effects, Energy Minimization and Performance Maximization (July 13, 2010)

Leakage has become an increasing fraction of processor power with each technology node. As leakage is strongly temperature dependent, processor power dissipation can be reduced by increasing fan/blower power to provide air at a higher volume flow rate and/or pressure drop. A global optimum can be achieved as a function of the leakage and heatsink characteristics.

Processor frequency is strongly dependent on temperature and voltage. The voltage dependence is approximately proportional, while temperature dependence has reduced with each technology node. In the near future, the temperature dependence may near zero and possibly even result in reduced frequency at reduced temperature. Even in such a case, if the processor voltage is increased at reduced temperature, which is in turn achieved by increased fan/blower power, energy can be minimized and performance maximized at lower temperatures. A parametric study encompassing past, present and future ranges of leakage and temperature effects is presented.

 

 

David Copeland is a Thermal Engineer working in the Packaging Technology department of Oracle's Microelectronics Group, developing packaging and cooling technology for UltraSPARC processors and the systems which use them. Areas of development include thermal interfaces, heat spreading materials, single-phase and phase-change liquid cooling, and data center cooling. He received his BS from Massachusetts Institute of Technology, MS from Stanford University and DrEng from Tokyo Institute of Technology, all in Mechanical Engineering.

Before coming to Sun in 2005, he worked in packaging and cooling at IBM, Hitachi and Fujitsu, and in heatsink development and design at Intricast, Sumitomo and Showa Aluminum. David belongs to ASME, IEEE and IMAPS, and is a frequent participant at conferences on electronics cooling.


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Marlin Vogel, Director of Business Development, Electronic Cooling Solutions, Inc
 

Tower & Low Profile Heat Pipe Heat Sink and Self-Contained Pumped Coolant Systems (June 8, 2010)

In order to meet the next generation CPU thermal requirements with a phase change heat sink, three heat sink technologies and their associated prototypes will be described. Each of the heat sink technologies use internal liquid-to-vapor phase change to efficiently spread the local CPU power to the air-cooled fin structure. The three passive phase change heat sink technologies are: multiple embedded heat pipes; vapor chamber base, and a hybrid vapor chamber / multiple tower heat pipes. Maintaining the same CPU module spatial envelope and air flow requirements for follow-on CPU designs in air-cooled servers will require on board, self contained, pumped coolant solutions that incorporate micro-channel cold plates with relatively low coolant pressure loss due to the current practical performance limitations of the passive phase change heat sink evaporator and condenser. Three pumped coolant technologies and their associated prototypes that met the increased thermal performance requirements will be described.

Typically in the past, if two heat sink technologies met the thermal performance requirements along with meeting the reliability performance requirements, the least expensive technology would be utilized. In the future, heat sink thermal performance specifications will consider including the impact of energy cost savings attained through reduced server air flow rate requirements if utilizing a superior heat sink technology warrants a potential increase in heat sink cost.

 

Marlin Vogel joined Electronic Cooling Solutions as the Director of Business Development in January, 2010. Marlin was a Sr. Staff level engineer at Sun Microsystems, where he conducted research, development, and productizing thermal technologies for CPU applications for 18 years, beginning in 1991. He lead the CPU module and system thermal development efforts for the high end sparc servers since 2002. Prior to joining Sun Microsystems Marlin was a member of the General Dynamics Thermodynamics Analysis group for 7 years, serving as co-leader of the thermal design effort for a Navy stealth jet aircraft engine exhaust.

Marlin obtained his Mechanical Engineering degree in 1979 and his M.S. degree in 1984 from the University of Wisconsin – Milwaukee and has authored several conference and journal papers on electronic cooling, and has been awarded 11 patents on electronic cooling inventions.


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Howard Harrison, President of Distributed Thermal Systems (DTS) Ltd.
 

Using Flow Optimizers to Save Cooing Fan Power (May 11, 2010)

The green data center initiative has increased everyone's awareness of power consumption. Cooling fans, although small relative to CRAC units and other large components, typically consume 5 to 15 % of server power. The number is even higher for series fan configurations, as performance has traditionally suffered due to the swirl between the fans. This talk will focus on the use of DTS flow optimizers to increase the efficiency of the series configuration beyond that of the underlying fans, thereby enhancing performance beyond the two fan theoretical limit. In most cases this will allow fan power to be reduced by ~20% while still achieving the required operating point. The latent thermal headroom may be used to accommodate future upgrades and increases in component density, without changing the fans.

An introduction to flow optimizers will be followed by a review of performance and efficiency results from a variety of fan sizes, designs and manufacturers. Then two brief case studies will highlight actual power savings and latent thermal headroom results for 1U and large format servers. Additional examples will include blower replacement and extreme static pressure configurations. Finally, the presentation of a general design methodology for implementing flow optimizers will be followed by an open discussion and Q&A.

 

Howard Harrison is the founder and President of Distributed Thermal Systems (DTS) Ltd., which has developed the flow optimizer technology in conjunction with the University of Waterloo. Prior to that he spent 14 years in the systems industry with Hewlett Packard and Digital Equipment Corporation. Howard earned a BSc. in Electrical Engineering from Queen's University as well as an MBA from the University of Toronto.

He holds several patents and patents pending, and has co-authored a variety of papers on the subject matter, most recently at SEMITHERM 2010 in San Jose.


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Ihab Andre Ali, Vice President of Thermal Products, Pipeline Micro, Inc
 

Challenges of Thermal Management and Design of Compact 3-D Microsystems - An Integrated System-Level Approach with Focus on Discrete Technologies (April 13, 2010)

The talk provides an overall review of thermal design performance limitations and thermal management techniques covering 3-D Microsystems with focus on mobile and handheld products. Thermal challenges are discussed including a key thermal design parameter concerning outer skin temperature limits based on natural convection and radiation with the ambient. Passive conduction techniques to increase the internal thermal performance of boards, substrates and IC packages are discussed. The talk provides an overview on internal IC's thermal performance enhancements utilizing liquid cooling. The discussion walks through a numerical example introducing an efficient microchannel pumped liquid cooled system for compact electronic form factors. The performance of the liquid cooled system is discussed at length and compared to conventional heat pipe based thermal architecture. Tradeoffs of various system related parameters are discussed in details. The talk while showing the benefit of liquid cooling in general, it focuses on the importance of taking an integrated system approach for thermal design of systems. The role of liquid cooling of increasing systems thermal performance can be significantly enhanced when factoring into the design and optimization the above system parameters.

 

 

Andre is currently vice president of thermal products at Pipeline Micro, Inc., an advanced electronic cooling and micro fabrication startup. Andre is a founder of Rola Technologies, a technical, market and product strategy consulting company in electronics thermal design and energy efficiency markets. He is a former chief thermal architect at Apple where he is credited for leading and innovating thermal technologies and design architectures for Apple's MacBook, MacBook Pro, MacBook Air, iMac, iPhone and other platforms. He is a former thermal technology engineer at Intel's mobile product group. His interests and research focus are in electronics thermal management and control, energy efficiency, renewable energy and environmental impact.


Andre is an inventor of over 20 patents and applications and publisher of numerous papers in the field of thermal management and heat transfer. He also served as keynote speaker, panelist and chair at various conferences and forums worldwide. Andre has a BS in civil engineering from Damascus University and MS in mechanical engineering from WPI.


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Magnus Herrlin, President, ANSIC, Inc.
 

Thermal Design of Data Centers to Safeguard the Electronic Equipment (March 9, 2010)

Electronic equipment manufacturers guarantee the thermal design of their products. They specify the required air intake temperatures to satisfy the cooling requirements. The thermal designer of the data center room ensures that the air drawn into the equipment meets or exceeds the manufacturers' specifications. Both the manufacturers and the data center designer need to understand the well-defined thermal interface between the equipment and the room. This presentation reviews methods and tools for designing and maintaining effective thermal equipment environments.

 

 

Dr. Magnus K. Herrlin is President of ANCIS Incorporated, a San Francisco based consultancy providing thermal and energy solutions for data centers and telecom central offices. Prior to establishing ANCIS, he served ten years as Principal Scientist with Bell Communications Research where he led efforts in optimizing energy and cooling efficiency of equipment rooms. Earlier, he served six years as Visiting Scientist with Lawrence Berkeley Laboratory (LBL).

Recent high-profile activities include:
 >Lead of the development of the Data Center Certified Energy Practitioner (DC-CEP) Program for the Department of Energy (DOE)
 >Provided CFD modeling and analysis of the first U.S. pre-qualified Platinum LEED data center for Advanced Data Centers (ADC)
 >Developed air-management solutions for the next Supercomputer Center at Lawrence Berkeley National Laboratory (LBNL).


Magnus is a Member of ASME and ASHRAE. Magnus holds a Ph.D. and an M.S. in Mechanical Engineering and is a Certified Energy Manager (CEM) by the Association of Energy Engineers.

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Tom Tarter, Proprietor and Principal Engineer, Package Science Services
 

Design of High Density Packaging: Tools and Knowledge (February 9, 2010)

Packaging of complex silicon devices requires a deep knowledge of many aspects of high-technology engineering disciplines. As an example, packaging a high lead-count chip requires knowledge of electrical, thermal, mechanical, chemical and manufacturing engineering. These disciplines must be known and must be used in the conceptualization, design and implementation of any package design. Complex systems many times require more than one die in the package. These chips can be stacked or arrayed onto a substrate to increase functionality and reduce size and cost, driving the complexity of the package beyond the capability of simple drawings and 2D design tools.

 

 

Mr. Tom Tarter is the proprietor and principal engineer of Package Science Services. He was a working professional in the area of thermal management and electrical characterization of packaging structures. He spent over 16 years at Advanced Micro Devices (Sunnyvale, CA) in package characterization and left as a Senior Member of the Technical Staff. After a short time as Director of BGA Package Engineering and Design at Advanced Interconnect Technology (Pleasanton, CA) he was responsible for thermal management, temperature control, and package development at Neo Photonics Corporation (San Jose / Fremont, CA). His knowledge of microelectronic and optical packaging spans this career and he is a noted expert on thermal and electrical characterization of packages, both in the microelectronic and optoelectronic regimes.


Tom has authored or co-authored over 20 published papers and numerous short courses and lectures on thermal and electrical phenomenon in microelectronic packaging and most recently in optoelectronic packaging. He has presented short courses and technical papers at conferences and technical meetings around the world. An invited lecturer and author, he has also lectured at graduate level short courses on micro- and opto-electronic packaging at UC Santa Cruz extension and San Jose State University.

Tom chaired the JEDEC JC15.1 task group on thermal standards for five years, and was general chair of the JC15 thermal and electrical characterization standards group for two years. He was general chair of the semiconductor heat transfer conference SemiTherm XIII, and serves on the executive committee of SemiTherm to date. He is also vice-technical chair for SEMI-International Electronics Manufacturing Technology Conference and is the technical program chair for Wescon 2003. Tom was the chapter chair for the IEEE Silicon Valley Chapter of CPMT. He has worked with the IEEE/CPMT for several years and has an excellent track record of engineering community service. Tom is also a member of IEEE and of the local CPMT and LEOS chapters.


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Guy Wagner, Thermal Consulting Engineer, Electronic Cooling Solutions Inc.,
 

Designing with Thermoelectric Coolers and Generators (January 12, 2010)

With increasing interest in solid-state cooling and power generation, the use of Thermoelectric Coolers (TECs) and Thermoelectric Generators (TEGs) is on the upswing. This presentation will cover the advantages and limitations of designing with TEC and TEGs. Techniques will be demonstrated showing how to efficiently use iterative techniques within a spreadsheet to effectively run a transient thermal analysis involving a TEC. Also demonstrated will be the use of the TEC SmartPart model within Flotherm to analyze the performance of a system using a TEC.

 

 

Mr. Wagner has over 35 years experience in the electronics industry. His experience includes: IC and system cooling and packaging technology, disk drive design, computer system design, and design of telephone switching systems. Mr. Wagner, an expert in cooling of electronics systems and IC packages, has authored 16 papers and talks at international conferences on this subject and has 26 patents. He is currently a consultant and the owner of RM laboratories. As a consultant he has provided thermal management support to a number of Electronic Cooling Solutions customers as well as to Hewlett Packard, Dell Computers and Vitesse Semiconductors.


Guy Wagner was previously the Director of Engineering for Cornice Reference Designs where he was responsible for the mechanical design of very small form factor (1 inch) hard drive products as well as the world’s smallest MP3 player with a hard drive.

Prior to joining Cornice, he held the position of Chief Scientist for the HP/Agilent Technologies PolarLogic Business unit. Other positions that he held at HP included: Technical Contributor within the HP Work Station Division where he was responsible for the thermal design and management of all HP workstation products and Member of the Technical Staff in Fort Collins where he developed packaging, thermal solutions, and assembly processes for the world’s first 32 bit microprocessor and the first Pin Grid Array and BGA packages.

Prior to joining HP Mr. Wagner held a position as a Member of the Technical Staff at AT&T Bell Laboratories where he was a lead engineer and provided thermal and mechanical design expertise to teams working on telephone switching equipment.

Mr. Wagner received his MS in Mechanical Engineering from Iowa State University.


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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
 

HiPwr LED Thermal Characterization – Methods and Issues (December 8, 2009)

The lack of industry standards for LED thermal measurements has given rise to confusion about thermal parameters and their applicability to application environments. While the basics of junction temperature measurements are applicable to HiPwr LEDs, defining the thermal measurement environment and test conditions in a manner consistent with application requirements are subject to much discussion. This presentation will discuss the methods and issues relative to thermal measurements and provide a industry status report on thermal issues.

 

 

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUniversity), M.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.


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Arun P. Raghupathy, Thermal Consulting Engineer, Electronic Cooling Solutions Inc.
 

Boundary-Condition-Independent (BCI) Compact Thermal Models (CTM) for CFD-based Thermal Analysis of Optical Transceivers (November 10, 2009)

A Compact Thermal Model is generated for a multi-heat source optical transceiver called Small Form-factor Pluggable package (SFP). When used in practical applications, the CTM is shown to be capable of predicting results with a maximum relative error of 7% with respect to the detailed model. In addition to presenting the methods, results and benefits of this study, the presentation will also outline goals for extension of this work to other types of optical transceivers.

 

 

Dr. Raghupathy has been with the company for three years. He has extensively worked and published in the areas of thermal management of electronics and reduced-order model development. He holds a doctoral degree in Mechanical Engineering from the University of Cincinnati, OH. He is also an active member of many technical organizations such as IEEE, ASME, AIAA and ASEI.

 


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George A Meyer IV, COO/CTO, Celsia Technologies
 

Understanding heat pipe and vapor chamber performance for design and modeling of thermal solutions (October 13, 2009)

Vapor chamber and heat pipe performance is often misunderstood which results is errors when trying to design thermal solutions using these products. The most common error is to apply an effective thermal conductivity number to these. By applying a thermal conductivity number it is inferring that the device has a linear resistance or delta-t. This is not the case.

This presentation will cover in detail the actual performance of these devices and how to use these numbers in designing thermal solutions.

 

 

Mr. Meyer is a seasoned industry veteran with over three decades experience in electronics thermal management. He has been with Celsia since December 2005, first as VP Sales and Marketing for the Americas and Europe regions and then as COO and CTO. In these roles, Mr. Meyer has been instrumental in establishing Asian operations, developing new technologies, key customer relationships, managing the product portfolio, and growing sales into the computer, telecommunications, LED lighting, medical, and military markets.

Prior to Celsia, he held various positions with Thermacore International (a leading supplier of thermal management solutions) including chairman and general manager of ThermacoreTaiwan and Korea, as well as vice president, worldwide sales and marketing. During his tenure, Meyer was credited with establishing the company’s Asian design and manufacturing facilities, developing patentable product designs, and growing relationships with leading technology companies such as Intel, Hewlett-Packard, Apple, Sun Microsystems and Silicon Graphics. He graduated from PennStateUniversity with a degree in Communications and holds an International Business Certificate from Franklin and MarshallCollege. Mr. Meyer is also a certified 6 Sigma Black Belt and holds 94 domestic and international patents/patents pending in the field of electronics thermal management.


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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
 

IC Thermal Measurements – According to JEDEC (September 8, 2009)

A gating item in the development of higher performance electronic systems is thermal management of integrated circuit (IC) power dissipation. Knowledge of the IC thermal performance is essential for developing cost-effective thermal management solutions. This presentation is designed for device, packaging and system design professionals who want an introduction to the "art" of integrated circuit thermal measurements in accordance with the JEDEC-standards. Details of junction temperature measurements and thermal test environment will be covered and reference sources will be provided.

 

 

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUnivers<.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.


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